MTD PS Specifikace stáhnout pdf (Strana 33)

Video

Vpixbinned

Reset

1 count = 8*(bin mode)*t

Clamp

Sample

A/D clock

PIX

t = 1/system clock

(Default Setting =200ns)

Pixel Rate Timing

Figure 12: Binning Mode Timing (2x2 binning shown)

In Binning Modes, the Frequency of the Reset, Clamp, Sample, A/D, and PIX clocks are decreased in order to allow charge

to accumulate on the output node of the CCD before being reset. See Application Note MTD/PS-0900 KAF Series Full-

Frame CCD Series Binning Mode Operation for more details on Full Frame CCD Binning.

Line Rate Timing

Number of pulses = bin mode +1

Number of pulses = bin mode

In Binning Modes, additional lines of charge are summed in the CCD’s horizontal register before being clocked to the

output node.

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 55 56

Žádné komentáře

MTD PS Specifikace Strana 33